This invention relates generally to an electrical wiring or conductor interconnect structure for a semiconductor device, integrated circuit or the like and in particular to a combination electrical wiring and passive element in an integrated circuit structure of a semiconductor device, such as, in a high resistance load type static RAM (SRAM) with a wiring interconnect including an integrated resistance for connection between a voltage source and a diffusion layer representing a terminal domain of an integrated active element, e.g., a MOSFET source or drain.
It is known in the prior art to provide integrated buried wiring interconnections in the fabrication of integrated circuits, such as, for example in the case of high resistance load type static RAM's or SRAM. One such example is disclosed in Japanese Patent Laid Open No. 130461/1982 and is exemplified in FIGS. 3 and 4. In order to fully appreciate the present invention, it is first desirable to discuss the state of the art relative to wiring interconnects in conventional high resistance polycrystalline silicon load type memory cells in order to better understand and appreciate the improvements brought about by the present invention. FIG. 4 illustrates the schematic representation of a conventional high resistance polycrystalline silicon load type memory cell comprising a flip flop for storing information with an output of one of two inverters, comprising series connected MOSFET Q.sub.1 and resistance R.sub.1 and series connected MOSFET Q.sub.2 and resistance R.sub.2, with each inverter connected as an input to the other. These flip flop circuits are combined with two switching MOSFETS's Q.sub.3 and Q.sub.4 connected to the write line (WL) for exchanging information externally of the cell via data lines DL and bar DL.
FIG. 3 illustrates a cross sectional portion of the integrated circuit structure for the storage FF circuit schematic shown in FIG. 4. The structure comprises a p-type silicon substrate upon which are formed regions of field insulating film 2, e.g., SiO.sub.2, beneath which are formed p-type channel stopper domains 3 to prevent the formation of parasitic channels. A gate insulating film 4, for example SiO.sub.2, is provided on the surface of each active element domain comprising Q.sub.1 through Q.sub.4, which domains are surrounded by field insulating film 2. Active domains shown in the FIG. 3 cross section disclose only MOSFET's Q.sub.1 and Q.sub.3.
A word line of predetermined form comprises a double layer film of polycrystalline silicon film 5 and high temperature or fusing point metal silicide or polycide film 6, which form gate electrode 7 and the gate for MOSFET Q.sub.3 bounded by side walls 11. These films are directly deposited on gate insulating film 4 and field insulating film 2. An n.sup.+ -type source domain 9 and n.sup.+ -type drain domain 10 are formed relative to each active element comprising a MOSFET, and are surrounded by field insulating film 2, and are in alignment with a word line, WL, gate electrode 7 and grounding conductor SL.
An interlayer insulating film 12, for example SiO.sub.2, is deposited over the double layer films 5, 6 and MOSFET's Q.sub.1 and Q.sub.3. A first contact hole 16 is then formed in interlayer insulating film 12 and thereafter a wiring layer 15 comprising a polycrystalline silicon film of predetermined form is deposited thereon. Wiring layer 15 includes n.sup.+ -type polycrystalline regions 15A and 15B and high resistance polycrystalline silicon resistances R.sub.1, R.sub.2 wherein, as seen in FIG. 3, only R.sub.2 is visible. Region R.sub.1 or R.sub.2 comprise an intrinsic polycrystalline silicon film 15C, which is integral with regions 15A and 15B of n.sup.+ -type polycrystalline film and all together form wiring layer 15. Next, a second interlayer insulating film 17, for example, a PSG film, is formed on wiring layer 15 followed by the deposition of data lines DL and bar DL (only line DL is visible in FIG. 3). Data lines DL and bar DL are connected respectively to drain domains 10 of MOSFET's Q.sub.3 and Q.sub.4 via the formed contact hole 21, as shown relative to Q.sub.3 in FIG. 3.
Resistance R.sub.1, R.sub.2 may be formed as follows. Wiring layer 15 is first deposited as a nondoped or intrinsic polycrystalline silicon film over the surface of interlayer insulating film 12. Next, a portion of the deposited intrinsic polycrystalline silicon film to function as a high resistance polycrystalline silicon resistance is covered by a masking layer and the remaining portions of layer 15 are exposed to a diffusion process with an impurity, such as, phosphorous (P) or arsenic (As) and ion implantation or other type of incorporation method. The masking layer is then removed, producing a polycrystalline silicon film 15 having a pattern of predetermined form comprising wiring or conductor sections 15A and 15B of n.sup.+ polycrystalline Si film, enhanced in conductivity by introduction of phosphorous or arsenic, and high resistance, intrinsic polycrystalline silicon regions 15C forming resistance R.sub.1 and R.sub.2.
Under present practice, the sizes of the polycrystalline silicon resistances R.sub.1 and R.sub.2 are determined by the spatial relation between contact hole 16 and power source V.sub.DD at the other end of wiring layer 15. Thus, as best illustrated in FIG. 4, resistances R.sub.1, R.sub.2 are connected to the source domains of MOSFET's Q.sub.1 through Q.sub.4 via wiring layer 15. The other ends of resistances R.sub.1, R.sub.2 are connected to power source V.sub.DD. The drains of MOSFET's Q.sub.1 and Q.sub.2 are connected to ground. Word line, WL, is connected to the gate electrodes of MOSFET's Q.sub.3 and Q.sub.4 and data lines DL and bar DL are connected to the drains of MOSFET's Q.sub.3 and Q.sub.4 via contact hole 21.
There remains, however, a problem in connection with the above described memory cell structure in that a refined construction and reduction in integrated circuit scale is not realizable. This problem is exemplified in the disclosure of Yoshio Sakai, "CMOS-SRAM Process Device Art", 28th Semiconductor Special Course Draft, pp. 69-114, wherein it is explained, that as the size of resistances R.sub.1 and R.sub.2 are shortened to refine the scale of the transistor structure, their resistance values become rapidly low. This is illustrated in the diagram of FIG. 5. Therefore, a desired high resistance value is difficult to obtain or retain since resistance values will be naturally reduced in value with any reduction in the integrated circuit scale. As a result, in the particular case of a SRAM, the consumption current during standby will accordingly increase. Therefore, a certain reasonable size, currently about 3 microns or more, is necessary, which is a big obstacle toward the realization of a refined memory cell construction and a reduction in memory cell scale. Further, it is presently believed that, in the future, the size of such a memory cell will be governed by the required sizes of the resistance R.sub.1 and R.sub.2 and, as a result, this problem of scale will become even more intensified.